Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

65

Voted

ASPDAC
1999
ACM

84views Hardware» more ASPDAC 1999»

Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach

15 years 7 months ago

Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach

Download www.cecs.uci.edu

Hidehisa Nagano, Takayuki Suyama, Akira Nagoya

Real-time Traffic

ASPDAC 1999 | Hardware |

claim paper

Related Content

» A New Class of Efficient BlockIterative Interference Cancellation Techniques for Digital C...

» On Some New Approaches to Practical SlepianWolf Compression Inspired by Channel Coding

» A New Rotation Search for Dependent RateDistortion Optimization in Video Coding

» Statistical Simulator for Block Coded Channels with Long Residual Interference

» Highthroughput bayesian computing machine with reconfigurable hardware

» Highperformance CUDA kernel execution on FPGAs

» Automatic systemC design configuration for a faster evaluation of different partitioning a...

» Null Keys Limiting Malicious Attacks Via Null Space Properties of Network Coding

» TimeFrequency Cepstral Features and Heteroscedastic Linear Discriminant Analysis for Langu...

Post Info
More Details (n/a)

Added	02 Aug 2010
Updated	02 Aug 2010
Type	Conference
Year	1999
Where	ASPDAC
Authors	Hidehisa Nagano, Takayuki Suyama, Akira Nagoya

Comments (0)