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80

VLSID
1997
IEEE

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Optimal Clock Period for Synthesized Data Paths

15 years 7 months ago

Optimal Clock Period for Synthesized Data Paths

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A. R. Naseer, M. Balakrishnan, Anshul Kumar

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VLSI | VLSID 1997 |

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Added	06 Aug 2010
Updated	06 Aug 2010
Type	Conference
Year	1997
Where	VLSID
Authors	A. R. Naseer, M. Balakrishnan, Anshul Kumar

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