Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits

This paper presents 3LSSD, a novel, easilyautomatable approach for scan insertion and ATPG of asynchronous circuits. 3LSSD inserts scan latches only into global circuit feedback paths, leaving the local feedback paths of asynchronous state-storing gates intact. By employing a three-phase LSSD clocking scheme and complemented by a novel ATPG method, our approach achieves industrial quality testability with significantly less area overhead testing the same number of faults compared to full-scan LSSD. The effectiveness of our approach is demonstrated on an asynchronous SOC interconnection fabric, where our 3LSSD ATPG tool achieved over 99% test coverage.

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards
• Keywords: Asynchronous State-storing Gates, DATE 2004, Feedback Paths, Hardware, Inserts Scan Latches