Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

76

Voted

IEICET
2006

favoriteEmaildiscussreport

77views more IEICET 2006»

Trends of On-Chip Interconnects in Deep Sub-Micron VLSI

15 years 10 days ago

Trends of On-Chip Interconnects in Deep Sub-Micron VLSI

Download www28.cs.kobe-u.ac.jp

Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kaw

Real-time Traffic

IEICET 2006 |

claim paper

Related Content

» On Thermal Effects in Deep SubMicron VLSI Interconnects

» Variationaware analysis savior of the nanometer era

» Adaptive Channel Buffers in OnChip Interconnection Networks A Power and Performance Analy...

» Design Methodologies and Architecture Solutions for HighPerformance Interconnects

» Information theoretic approach to address delay and reliability in long onchip interconnec...

» Interconnect design for deep submicron ICs

» ETAM Extended Transition Activity Measure for Low Power Address Bus Designs

» Networks on Silicon Blessing or Nightmare

Post Info
More Details (n/a)

Added	12 Dec 2010
Updated	12 Dec 2010
Type	Journal
Year	2006
Where	IEICET
Authors	Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai

Comments (0)