Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

66

Voted

IEICET
2010

86views more IEICET 2010»

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture

15 years 2 months ago

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture

Download www.kameyama.ecei.tohoku.ac.jp

Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama

Real-time Traffic

IEICET 2010 |

claim paper

Related Content

» An implementation of an asychronous FPGA based on LEDRfourphasedualrail hybrid architectur...

» Rapid estimation of power consumption for hybrid FPGAs

» A lowpower FPGA based on autonomous finegrain powergating

» YARDS FPGAMPU Hybrid Architecture for Telecommunication Data Processing

» Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks

» A reconfigurable architecture for hybrid CMOSNanodevice circuits

» Architectural Frameworks for MPP Systems on a Chip

» Monolithically stackable hybrid FPGA

» Evaluating Large SystemonChip on MultiFPGA Platform

Post Info
More Details (n/a)

Added	26 Jan 2011
Updated	26 Jan 2011
Type	Journal
Year	2010
Where	IEICET
Authors	Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama

Comments (0)