Efficient Place and Route for Pipeline Reconfigurable Architectures

In this paper, we present a fast and eficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, and fairly eficient. We represent pipeline reconfigurable architectures by a generalized VLI W-like model. The complex architectural constraints are effectively expressed in terms of a single graph parameter: the routing path length (RPL). Compiling to our model using RPL, we demonstrate fast compilation times and show speedups of between lox and 200x on a pipeline reconfigurable architecture when compared to an UltraSparc-II.

• Type: Conference
• Year: 2000
• Where: ICCD
• Authors: Srihari Cadambi, Seth Copen Goldstein
• Keywords: Fast Compilation Times, Hardware, ICCD 2000, Pipeline Reconfigurable Architectures, Single Graph Parameter