Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

109

Voted

ICCAD
2004
IEEE

123views Hardware» more ICCAD 2004»

Logical effort based technology mapping

16 years 10 days ago

Logical effort based technology mapping

Download www.ece.umn.edu

We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended to solve the loaddistribution problem for circuits with fanout. On average, benchmark circuits mapped using our approach are 25.39% faster than the solutions obtained from SIS.

Shrirang K. Karandikar, Sachin S. Sapatnekar

Real-time Traffic

Benchmark Circuits | Fanout-free Circuits | Hardware | ICCAD 2004 | Library-based Technology Mapping |

claim paper

Related Content

» Physical Extension of the Logical Effort Model

» The HCONE Approach to Ontology Merging

» Technology Mapping Using Fuzzy Logic

» Technology Mapping for Reliability Enhancement in Logic Synthesis

» Exact Treebased FPGA Technology Mapping for Logic Blocks with Independent LUTs

» IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level

» DAG based libraryfree technology mapping

» Delay Minimal Decomposition of Multiplexers in Technology Mapping

» Power consumption of logic circuits in ambipolar carbon nanotube technology

Post Info
More Details (n/a)

Added	16 Mar 2010
Updated	16 Mar 2010
Type	Conference
Year	2004
Where	ICCAD
Authors	Shrirang K. Karandikar, Sachin S. Sapatnekar

Comments (0)