Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
PDF Tools
Image Tools
Text Tools
OCR Tools
Symbol and Emoji Tools
On-screen Keyboard
Latex Math Equation to Image
Smart IPA Phonetic Keyboard
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
Free Online Productivity Tools
i2Speak
i2Symbol
i2OCR
iTex2Img
iWeb2Print
iWeb2Shot
i2Type
iPdf2Split
iPdf2Merge
i2Bopomofo
i2Arabic
i2Style
i2Image
i2PDF
iLatex2Rtf
Sci2ools
80
Voted
ICCAD
2002
IEEE
98
views
Hardware
»
more
ICCAD 2002
»
Topologically constrained logic synthesis
15 years 11 months ago
Download
www.eecs.berkeley.edu
Subarnarekha Sinha, Alan Mishchenko, Robert K. Bra
Real-time Traffic
Hardware
|
ICCAD 2002
|
claim paper
Related Content
»
Using Constrained Intuitionistic Linear Logic for Hybrid Robotic Planning Problems
»
Topology aware mapping of logic functions onto nanowirebased crossbar architectures
»
A Hashbased Approach for Functional Regularity Extraction During Logic Synthesis
»
Synthesis for Logical Initializability of Synchronous Finite State Machines
»
Sequential synthesis using S1S
»
Dominatorbased partitioning for delay optimization
»
CapacityConstrained Design of Resilient MultiTier Wireless Mesh Networks
»
RF CMOS circuit optimizing procedure and synthesis tool
»
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
more »
Post Info
More Details (n/a)
Added
17 Mar 2010
Updated
17 Mar 2010
Type
Conference
Year
2002
Where
ICCAD
Authors
Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
Comments
(0)
Researcher Info
Hardware Study Group
Computer Vision