Dynamic zero compression for cache energy reduction

Dynamic Zero Compression reduces the energy required for cache accesses by only writing and reading a single bit for every zero-valued byte. This energy-conscious compression is invisible to software and is handled with additional circuitry embedded inside the cache RAM arrays and the CPU. The additional circuitry imposes a cache area overhead of 9% and a read latency overhead of around two FO4 gate delays. Simulation results show that we can reduce total data cache energy by around 26% and instruction cache energy by around 10% for SPECint95 and MediaBench benchmarks. We also describe the use of an instruction recoding technique that increases instruction cache energy savings to 18%.

• Type: Conference
• Year: 2000
• Where: MICRO
• Authors: Luis Villa, Michael Zhang, Krste Asanovic
• Keywords: Cache, Cache Energy, Hardware, Instruction Cache Energy, MICRO 2000