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NOCS
2007
IEEE

Fast, Accurate and Detailed NoC Simulations

13 years 11 months ago
Fast, Accurate and Detailed NoC Simulations
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed. Cycle and bit accurate simulation is necessary when the actual router’s RTL description needs to be evaluated and verified. However, extensive simulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming. In this paper we describe a simulation method to simulate large parallel homogeneous and heterogeneous network-on-chips on a single FPGA. The method is especially suitable for parallel systems where lengthy cycle and bit accurate simulations are required. As a case study, we use a NoC that was modelled and simulated in SystemC. We simulate the same NoC on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we ach...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where NOCS
Authors Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit
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