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DATE
2007
IEEE

Analytical router modeling for networks-on-chip performance analysis

14 years 6 months ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we first present a generalized router model and then utilize this novel model for doing NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.
Ümit Y. Ogras, Radu Marculescu
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where DATE
Authors Ümit Y. Ogras, Radu Marculescu
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