A formal executable semantics of Verilog

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A formal executable semantics of Verilog
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilogbased tools; e.g., simulators, test generators, and verification tools. Our semantics applies equally well to both synthesizeable and behavioral designs and is given in a familiar, operational-style within a logic providing important additional benefits above and beyond static formalization. In particular, it is executable and searchable so that one can ask questions about how a, possibly nondeterministic, Verilog program can legally behave under the formalization. The formalization should not be seen as the final word on Verilog, but rather as a starting point and basis for community discussions on the Verilog semantics.
Patrick O'Neil Meredith, Michael Katelman, Jos&eac
Added 14 Feb 2011
Updated 14 Feb 2011
Type Journal
Year 2010
Authors Patrick O'Neil Meredith, Michael Katelman, José Meseguer, Grigore Rosu
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