303 search results - page 1 / 61 » A formal executable semantics of Verilog |
87
Voted
MEMOCODE
2010
IEEE
14 years 7 months ago
2010
IEEE
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
FDL
2004
IEEE
15 years 1 months ago
2004
IEEE
We present a rigorous but transparent semantics definition of SystemVerilog that covers processes with blocking and non-blocking statements as well as their interaction with the s...
80
Voted
FTRTFT
1998
Springer
15 years 1 months ago
1998
Springer
73
Voted
MEMOCODE
2005
IEEE
15 years 3 months ago
2005
IEEE
The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are ch...
FMCAD
2000
Springer
15 years 1 months ago
2000
Springer
Abstract. Since the advent of model checking it is becoming more common for languages to be given a semantics in terms of transition systems. Such semantics allow to model check pr...