Framework for Fault Analysis and Test Generation in DRAMs

Abstract: With the increasing complexity of memory behavior, attempts are being made to come up with a methodical approach that employs electrical simulation to tackle the memory test problem. This paper describes a framework of algorithms and tools developed jointly by the Delft University of Technology and Infineon Technologies to systematically generate DRAM tests using Spice simulation. The proposed Spice-based test approach enjoys the advantage of being relatively inexpensive, yet highly accurate in describing the desired memory faulty behavior.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor
• Keywords: DATE 2005, Hardware, Memory Behavior, Memory Faulty Behavior, Memory Test Problem