Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation

: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection and electrical simulation. The new method shows how each stress should be applied to achieve a higher fault coverage of a given test, based on an understanding of the internal behavior of the memory. In addition, results of a fault analysis study, performed to verify the new optimization method, show its effectiveness. Key words: stresses, memory testing, test optimization, defect simulation.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter
• Keywords: DATE 2003, Fault Analysis Study, Hardware, Industrial Dram Test, Memory Testing