Heat-and-run: leveraging SMT and CMP to manage power density through the operating system

Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of supply voltage and thermal ability of packages to dissipate heat. Power density is characterized by localized chip hot spots that can reach critical temperatures and cause failure. Previous architectural approaches to power density have used global clock gating, fetch toggling, dynamic frequency scaling, or resource duplication to either prevent heating or relieve overheated resources in a superscalar processor. Previous approaches also evaluate design technologies where power density is not a major problem and most applications do not overheat the processor. Future processors, however, are likely to be chip multiprocessors (CMPs) with simultaneously-multithreaded (SMT) cores. SMT CMPs pose unique challenges and opportunities for power density. SMT and CMP increase throughput and thus on-chip heat, but also pr...

• Type: Conference
• Year: 2004
• Where: ASPLOS
• Authors: Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar
• Keywords: ASPLOS 2004, Overheated Cores, Power Density, Programming Languages, SMT Contexts