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ICCAD
1995
IEEE

PARAS: system-level concurrent partitioning and scheduling

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PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (called PARAS) which can exploit this interaction by solving the scheduling and partitioning problems concurrently are presented. PARAS maximizes the overall performance of the nal design and considers di erent chip con gurations and communication structures. Experiments, conducted with speci cations ranging in size from few to hundreds of operations, demonstrate the success of this approach.
Wing Hang Wong, Rajiv Jain
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where ICCAD
Authors Wing Hang Wong, Rajiv Jain
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