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ICCAD
1995
IEEE
77views Hardware» more  ICCAD 1995»
13 years 8 months ago
PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
Wing Hang Wong, Rajiv Jain
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
13 years 8 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
ICCAD
1995
IEEE
96views Hardware» more  ICCAD 1995»
13 years 8 months ago
Delay optimal partitioning targeting low power VLSI circuits
Hirendu Vaishnav, Massoud Pedram
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
13 years 8 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 8 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
13 years 8 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
ICCAD
1995
IEEE
90views Hardware» more  ICCAD 1995»
13 years 8 months ago
Design-for-debugging of application specific designs
Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayash...
ICCAD
1995
IEEE
84views Hardware» more  ICCAD 1995»
13 years 8 months ago
Statistical behavioral modeling and characterization of A/D converters
This paper presents a method to characterize Nyquist rate A/D converters based on the use of a first order statistical behavioral model. The proposed model is derived from a very...
Eduardo J. Peralías, Adoración Rueda...