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ASPDAC
2000
ACM

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A programmable built-in self-test core for embedded memories

15 years 6 months ago

A programmable built-in self-test core for embedded memories

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Testing embedded memories is becoming an industry-wide concern with the advent of deep-submicron technology and system-on-chip applications. We present a prototype chip for a programmable built-in self-test (BIST) design that is used for testing embedded memories, especially DRAMs. The BIST chip supports various memory test algorithms by a novel controller and sequencer design. The area of the core circuit is about 1, 020

Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu

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ASPDAC 2000 | BIST Chip | Hardware | Programmable Built-in Self-test | Testing Embedded Memories |

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Added	24 Aug 2010
Updated	24 Aug 2010
Type	Conference
Year	2000
Where	ASPDAC
Authors	Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu

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