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ICCAD
2006
IEEE

Simultaneous power and thermal integrity driven via stapling in 3D ICs

14 years 3 months ago
Simultaneous power and thermal integrity driven via stapling in 3D ICs
The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first in-depth study on simultaneous power and thermal integrity driven viastapling in 3D design. The transient temperature and supply voltage violations are calculated by a structured and parameterized model reduction, which also generates parameterized temperature and voltage violation sensitivities with respect to the via pattern and density. Using parameterized sensitivities, an efficient yet effective greedy optimization is presented to optimize power and thermal integrity simultaneously. Experiments with two active device layers show that compared to sequential power and thermal optimization using steady-state thermal analysis, sequential optimization using transient thermal analysis reduces non-signal
Hao Yu, Joanna Ho, Lei He
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2006
Where ICCAD
Authors Hao Yu, Joanna Ho, Lei He
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