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The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...

Kourosh Gharachorloo, Anoop Gupta, John L. Henness...

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138

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ASPLOS
1991
ACM

139views Programming Languages» more ASPLOS 1991»

LimitLESS Directories: A Scalable Cache Coherence Scheme

15 years 8 months ago

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Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...

David Chaiken, John Kubiatowicz, Anant Agarwal

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138

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ASPLOS
1991
ACM

130views Programming Languages» more ASPLOS 1991»

The Cache Performance and Optimizations of Blocked Algorithms

15 years 8 months ago

Download www.ece.cmu.edu

Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchies. Instead of operating on entire rows or columns of an array, blocked algorith...

Monica S. Lam, Edward E. Rothberg, Michael E. Wolf

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134

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ASPLOS
1991
ACM

125views Programming Languages» more ASPLOS 1991»

Code Generation for Streaming: An Access/Execute Mechanism

15 years 8 months ago

Download www.cs.virginia.edu

Access/execute architectures have several advantages over more traditional architectures. Because address generation and memory access are decoupled from operand use, memory laten...

Manuel E. Benitez, Jack W. Davidson

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