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The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...

Kourosh Gharachorloo, Anoop Gupta, John L. Henness...

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195

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ASPLOS
1991
ACM

139views Programming Languages» more ASPLOS 1991»

LimitLESS Directories: A Scalable Cache Coherence Scheme

15 years 11 months ago

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Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...

David Chaiken, John Kubiatowicz, Anant Agarwal

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188

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ASPLOS
1991
ACM

119views Programming Languages» more ASPLOS 1991»

NUMA Policies and Their Relation to Memory Architecture

15 years 11 months ago

Download www.cs.rochester.edu

Multiprocessor memory reference traces provide a wealth of information on the behavior of parallel programs. We have used this information to explore the relationship between kern...

William J. Bolosky, Michael L. Scott, Robert P. Fi...

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183

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ASPLOS
1991
ACM

125views Programming Languages» more ASPLOS 1991»

Code Generation for Streaming: An Access/Execute Mechanism

15 years 11 months ago

Download www.cs.virginia.edu

Access/execute architectures have several advantages over more traditional architectures. Because address generation and memory access are decoupled from operand use, memory laten...

Manuel E. Benitez, Jack W. Davidson

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