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» 3D floorplanning with thermal vias
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ICCAD
2005
IEEE
118views Hardware» more  ICCAD 2005»
15 years 6 months ago
Thermal via planning for 3-D ICs
Heat dissipation is one of the most serious challenges in 3D IC designs. One effective way of reducing circuit temperature is to introduce thermal through-the-silicon (TTS) vias....
Jason Cong, Yan Zhang
MICRO
2006
IEEE
144views Hardware» more  MICRO 2006»
15 years 3 months ago
Die Stacking (3D) Microarchitecture
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
Bryan Black, Murali Annavaram, Ned Brekelbaum, Joh...
ASPDAC
2005
ACM
134views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Wire congestion and thermal aware 3D global placement
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
Karthik Balakrishnan, Vidit Nanda, Siddharth Easwa...
DATE
2009
IEEE
161views Hardware» more  DATE 2009»
15 years 4 months ago
Co-design of signal, power, and thermal distribution networks for 3D ICs
— Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solu...
Young-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad ...
3DIC
2009
IEEE
142views Hardware» more  3DIC 2009»
15 years 2 months ago
Electrical-thermal co-analysis for power delivery networks in 3D system integration
- In this paper, an electrical-thermal co-analysis method for power delivery networks in 3D system integration is proposed. For electrical analysis, temperature-dependent electrica...
Jianyong Xie, Daehyun Chung, Madhavan Swaminathan,...