8 search results - page 2 / 2 » A CMOS neural oscillator using negative resistance |
DATE
2005
IEEE
13 years 8 months ago
2005
IEEE
This paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog / RF circuits taking into account the role of the parasitic resis...
ISCAS
2006
IEEE
14 years 9 days ago
2006
IEEE
A Q-enhancement technique based on active com- vcci pensation of monolithic inductors for parallel resonant LC tanks Cp is presented. Narrowband Q-enhancement is achieved using a h...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...