158 search results - page 26 / 32 » A CP Scheduler for High-Performance Computers |
108
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ICS
2005
Tsinghua U.
15 years 6 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
112
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CF
2005
ACM
15 years 2 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
88
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IPPS
2007
IEEE
15 years 7 months ago
2007
IEEE
This paper investigates the utilization of the master-slave (MS) paradigm as an alternative to domain decomposition (DD) methods for parallelizing lattice gauge theory (LGT) model...
PPOPP
2005
ACM
15 years 6 months ago
2005
ACM
Efficient partitioning of parallel loops plays a critical role in high performance and efficient use of multiprocessor systems. Although a significant amount of work has been don...
FPL
2003
Springer
15 years 6 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...