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91
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ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
13 years 5 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
98
Voted
EMSOFT
2005
Springer
15 years 3 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
EH
2004
IEEE
118views Hardware» more  EH 2004»
15 years 1 months ago
Exploring Knowledge Schemes for Efficient Evolution of Hardware
There exist several approaches to improve the quality of evolution. In this paper, a priori design knowledge as a part of evolving systems is discussed. Further, experiments are r...
Jim Torresen
94
Voted
IPPS
2006
IEEE
15 years 3 months ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
ICCAD
2005
IEEE
131views Hardware» more  ICCAD 2005»
15 years 6 months ago
Code restructuring for improving cache performance of MPSoCs
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
Guilin Chen, Mahmut T. Kandemir