Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed ar...
Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah...
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
Phishing is a significant problem involving fraudulent email and web sites that trick unsuspecting users into revealing private information. In this paper, we present the design, ...
Jason I. Hong, Lorrie Faith Cranor, Yue Zhang 0002
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...