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DAC
2007
ACM

Scan Test Planning for Power Reduction

15 years 29 days ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can be used for reducing the power consumption during test. Here, we present an efficient algorithm for the automated generation of a test plan that keeps fault coverage as well as test time, while significantly reducing the amount of wasted energy. A fault isolation table, which is usually used for diagnosis and debug, is employed to accurately determine scan chains that can be disabled. The algorithm was successfully applied to large industrial circuits and identifies a very large amount of excess pattern shift activity. Categories and Subject Descriptors-- B.8.1 [Hardware]: Performance and Reliability Reliability, Testing and Fault-Tolerance General Terms-- Algorithms, Reliability Keywords-- Test planning, power during test
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2007
Where DAC
Authors Christian G. Zoellin, Hans-Joachim Wunderlich, Jens Leenstra, Michael E. Imhof, Nicolas Mäding
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