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DAC
2007
ACM
16 years 8 months ago
TROY: Track Router with Yield-driven Wire Planning
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
DAC
2005
ACM
16 years 8 months ago
Automatic generation of customized discrete fourier transform IPs
This paper presents a parameterized soft core generator for the discrete Fourier transform (DFT). Reusable IPs of digital signal processing (DSP) kernels are important time-saving...
Grace Nordin, Peter A. Milder, James C. Hoe, Marku...
DAC
2009
ACM
16 years 1 months ago
Beyond verification: leveraging formal for debugging
The latest advancements in the commercial formal model checkers have enabled the integration of formal property verification with the conventional testbench based methods in the o...
Rajeev K. Ranjan, Claudionor Coelho, Sebastian Ska...
RECONFIG
2009
IEEE
182views VLSI» more  RECONFIG 2009»
16 years 1 months ago
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...
Siddhartha Datta, Ron Sass
SLIP
2009
ACM
16 years 1 months ago
Floorplan-based FPGA interconnect power estimation in DSP circuits
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic