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FPL
2004
Springer
95views Hardware» more  FPL 2004»
15 years 5 months ago
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor
Abstract. This paper proposes an architecture that combines a contextswitching virtual configware/software SAT solver with an embedded processor to promote a tighter coupling betwe...
C. J. Tavares, C. Bungardean, G. M. Matos, Jos&eac...
FPL
2000
Springer
155views Hardware» more  FPL 2000»
15 years 3 months ago
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...
Valery Sklyarov
MAM
2007
157views more  MAM 2007»
14 years 11 months ago
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
Darrin M. Hanna, Michael DuChene
CODES
2003
IEEE
15 years 4 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
15 years 3 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani