84 search results - page 4 / 17 » A Configurable Logic Architecture for Dynamic Hardware Softw... |
127
Voted
ICCD
2006
IEEE
15 years 10 months ago
2006
IEEE
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
IPPS
2003
IEEE
15 years 6 months ago
2003
IEEE
This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence...
121
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FCCM
2005
IEEE
15 years 6 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
151
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DATE
1999
IEEE
15 years 5 months ago
1999
IEEE
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
132
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DAC
1997
ACM
15 years 5 months ago
1997
ACM
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...