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» A Decompression Architecture for Low Power Embedded Systems
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SBCCI
2003
ACM
96views VLSI» more  SBCCI 2003»
15 years 5 months ago
SoCIN: A Parametric and Scalable Network-on-Chip
Networks-on-Chip (NoCs) interconnection architectures to be used in future billion-transistor Systems-on-Chip (SoCs) meet the major communication requirements of these systems, of...
Cesar Albenes Zeferino, Altamiro Amadeu Susin
CODES
2002
IEEE
15 years 5 months ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia
103
Voted
DATE
2004
IEEE
131views Hardware» more  DATE 2004»
15 years 4 months ago
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
Anuja Sehgal, Krishnendu Chakrabarty
128
Voted
IWSOC
2003
IEEE
97views Hardware» more  IWSOC 2003»
15 years 5 months ago
Evaluating Template-Based Instruction Compression on Transport Triggered Architectures
In embedded systems, memory is one of the most expensive resources. Due to this, program code size has turned out to be one of the most critical design constraints. Code compressi...
Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio...
85
Voted
EMSOFT
2005
Springer
15 years 6 months ago
Using de-optimization to re-optimize code
The nature of embedded systems development places a great deal of importance on meeting strict requirements in areas such as static code size, power consumption, and execution tim...
Stephen Hines, Prasad Kulkarni, David B. Whalley, ...