714 search results - page 94 / 143 » A Decompression Architecture for Low Power Embedded Systems |
97
Voted
ISCA
1997
IEEE
15 years 4 months ago
1997
IEEE
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
106
Voted
ARC
2007
Springer
15 years 4 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
93
Voted
ASAP
2010
IEEE
15 years 2 months ago
2010
IEEE
In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication ...
SBACPAD
2009
IEEE
15 years 7 months ago
2009
IEEE
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
IPPS
2007
IEEE
15 years 6 months ago
2007
IEEE
The indexing of complex data and similarity search plays an important role in many application areas. Traditional centralized index structure can not scale with the rapid prolifer...