59 search results - page 3 / 12 » A Delay Model and Speculative Architecture for Pipelined Rou... |
117
Voted
CF
2008
ACM
15 years 7 days ago
2008
ACM
To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi...
144
Voted
ISCA
2012
IEEE
13 years 20 days ago
2012
IEEE
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
94
Voted
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
96
Voted
MICRO
2010
IEEE
14 years 8 months ago
2010
IEEE
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
111
Voted
HPCA
1995
IEEE
15 years 1 months ago
1995
IEEE
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...