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GLVLSI
1998
IEEE
83views VLSI» more  GLVLSI 1998»
15 years 2 months ago
A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits
Kaamran Raahemifar, Majid Ahmadi
DSN
2004
IEEE
15 years 2 months ago
Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits
This paper presents a novel circuit fault detection and isolation technique for quasi delay-insensitive asynchronous circuits. We achieve fault isolation by a combination of physi...
Christopher LaFrieda, Rajit Manohar
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
15 years 4 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...
DATE
2004
IEEE
142views Hardware» more  DATE 2004»
15 years 2 months ago
Eliminating False Positives in Crosstalk Noise Analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Mal...
ET
2010
98views more  ET 2010»
14 years 9 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...