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» A Distributed Platform for Mechanism Design
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2005
IEEE
117views Hardware» more  DATE 2005»
15 years 3 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
FITRAMEN
2008
14 years 11 months ago
A Fair and Dynamic Load-Balancing Mechanism
The current data network scenario makes Traffic Engineering (TE) a very challenging task. The ever growing access rates and new applications running on end-hosts result in more var...
Federico Larroca, Jean-Louis Rougier
CCGRID
2008
IEEE
15 years 2 days ago
High Performance Relay Mechanism for MPI Communication Libraries Run on Multiple Private IP Address Clusters
We have been developing a Grid-enabled MPI communication library called GridMPI, which is designed to run on multiple clusters connected to a wide-area network. Some of these clust...
Ryousei Takano, Motohiko Matsuda, Tomohiro Kudoh, ...
CF
2010
ACM
15 years 3 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
87
Voted
ICPP
2003
IEEE
15 years 3 months ago
A Hardware-based Cache Pollution Filtering Mechanism for Aggressive Prefetches
Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between proces...
Xiaotong Zhuang, Hsien-Hsin S. Lee