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DEXA
2009
Springer
138views Database» more  DEXA 2009»
15 years 4 months ago
Evaluating Non-In-Place Update Techniques for Flash-Based Transaction Processing Systems
Recently, flash memory is emerging as the storage device. With price sliding fast, the cost per capacity is approaching to that of SATA disk drives. So far flash memory has been ...
Yongkun Wang, Kazuo Goda, Masaru Kitsuregawa
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
15 years 3 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...
ARCS
2005
Springer
15 years 3 months ago
Towards Autonomic Networking Using Overlay Routing Techniques
With an ever-growing number of computers being embedded into our surroundings, the era of ubiquitous computing is approaching fast. However, as the number of networked devices incr...
Kendy Kutzner, Curt Cramer, Thomas Fuhrmann
SIBGRAPI
2003
IEEE
15 years 3 months ago
Using Efficient Visual Exploration Techniques to Evaluate Features for Content-Based Image Retrieval
This paper presents a novel visual approach to evaluate, in a fast and effective way, the development of new image feature extraction techniques concerning content-based image ret...
José Fernando Rodrigues Jr., César A...
ASPDAC
1999
ACM
113views Hardware» more  ASPDAC 1999»
15 years 2 months ago
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
C. K. Eem, J. W. Chong