Sciweavers

154 search results - page 8 / 31
» A Formal Verification Approach for IP-based Designs
Sort
View
123
Voted
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
15 years 5 months ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...
FMAM
2010
157views Formal Methods» more  FMAM 2010»
14 years 11 months ago
An Experience on Formal Analysis of a High-Level Graphical SOA Design
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
Maurice H. ter Beek, Franco Mazzanti, Aldi Sulova
EUROMICRO
1996
IEEE
15 years 6 months ago
A Graph Rewriting Approach for Transformational Design of Digital Systems
Transformational design integrates design and verification. It combines "correctness by construciion" and design creativity by the use ofpre-proven behaviour preserving ...
Corrie Huijs
120
Voted
ICWE
2005
Springer
15 years 7 months ago
The Role of Visual Tools in a Web Application Design and Verification Framework: A Visual Notation for LTL Formulae
As the Web becomes a platform for implementing complex B2C and B2B applications, there is a need to extend Web conceptual modeling to process-centric applications. In this context,...
Marco Brambilla, Alin Deutsch, Liying Sui, Victor ...
TAP
2008
Springer
144views Hardware» more  TAP 2008»
15 years 1 months ago
Integrating Verification and Testing of Object-Oriented Software
Formal methods can only gain widespread use in industrial software development if they are integrated into software development techniques, tools, and languages used in practice. A...
Christian Engel, Christoph Gladisch, Vladimir Kleb...