Sciweavers

1420 search results - page 278 / 284
» A Framework for Scheduler Synthesis
Sort
View
CASES
2006
ACM
15 years 3 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
RTAS
2005
IEEE
15 years 3 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
RTAS
2005
IEEE
15 years 3 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
PLDI
2005
ACM
15 years 3 months ago
Register allocation for software pipelined multi-dimensional loops
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
Hongbo Rong, Alban Douillet, Guang R. Gao
110
Voted
WAOA
2005
Springer
104views Algorithms» more  WAOA 2005»
15 years 3 months ago
The Online Target Date Assignment Problem
Abstract. Many online problems encountered in real-life involve a twostage decision process: upon arrival of a new request, an irrevocable firststage decision (the assignment of a...
Stefan Heinz, Sven Oliver Krumke, Nicole Megow, J&...