1420 search results - page 42 / 284 » A Framework for Scheduler Synthesis |
105
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DAC
2004
ACM
16 years 2 months ago
2004
ACM
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
131
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AHS
2007
IEEE
15 years 6 months ago
2007
IEEE
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...
117
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VLSID
2000
IEEE
15 years 6 months ago
2000
IEEE
The technique presented here achieves simultaneous optimization of schedule time and data path component cost within a structured data path architecture, using a genetic algorithm...
101
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DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
104
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DATE
2008
IEEE
15 years 8 months ago
2008
IEEE
This work addresses the issue of design optimization for faulttolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpoin...