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» A General S-Domain Hierarchical Network Reduction Algorithm
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DAC
2003
ACM
16 years 2 months ago
Distributed sleep transistor network for power reduction
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
Changbo Long, Lei He
108
Voted
MASCOTS
2007
15 years 3 months ago
Distance Reduction in Mobile Wireless Communication: Lower Bound Analysis and Practical Attainment
— The transmission energy required for a wireless communication increases superlinearly with the communication distance. In a mobile wireless network, nodal movement can be explo...
Yu Dong, Wing-Kai Hon, David K. Y. Yau, Jren-Chit ...
TMC
2011
203views more  TMC 2011»
14 years 8 months ago
Throughput Optimization in Mobile Backbone Networks
—This paper describes new algorithms for throughput optimization in a mobile backbone network. This hierarchical communication framework combines mobile backbone nodes, which hav...
Emily M. Craparo, Jonathan P. How, Eytan Modiano
117
Voted
IPSN
2003
Springer
15 years 7 months ago
Boundary Estimation in Sensor Networks: Theory and Methods
Sensor networks have emerged as a fundamentally new tool for monitoring spatially distributed phenomena. This paper investigates a strategy by which sensor nodes detect and estima...
Robert Nowak, Urbashi Mitra
109
Voted
FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
15 years 8 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson