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ARC
2009
Springer
134views Hardware» more  ARC 2009»
15 years 2 months ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
FPL
2009
Springer
107views Hardware» more  FPL 2009»
15 years 2 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...
ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
14 years 10 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
ETS
2011
IEEE
224views Hardware» more  ETS 2011»
13 years 9 months ago
AVF Analysis Acceleration via Hierarchical Fault Pruning
—The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way ...
Michail Maniatakos, Chandra Tirumurti, Abhijit Jas...
CLUSTER
2008
IEEE
14 years 11 months ago
Improving message passing over Ethernet with I/OAT copy offload in Open-MX
Abstract--Open-MX is a new message passing layer implemented on top of the generic Ethernet stack of the Linux kernel. Open-MX works on all Ethernet hardware, but it suffers from e...
Brice Goglin