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» A Hardware Packet Re-Sequencer Unit for Network Processors
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VSTTE
2005
Springer
13 years 12 months ago
Performance Validation on Multicore Mobile Devices
The validation of modern software systems on mobile devices needs to incorporate both functional and non-functional requirements. While some progress has been made in validating pe...
Thomas Hubbard, Raimondas Lencevicius, Edu Metz, G...
IEEEPACT
2008
IEEE
14 years 25 days ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
INFOCOM
2009
IEEE
14 years 1 months ago
Nuclei: GPU-Accelerated Many-Core Network Coding
—While it is a well known result that network coding achieves optimal flow rates in multicast sessions, its potential for practical use has remained to be a question, due to its...
Hassan Shojania, Baochun Li, Xin Wang
CASES
2009
ACM
14 years 28 days ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
ECRTS
2007
IEEE
14 years 22 days ago
Cache-Aware Timing Analysis of Streaming Applications
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
Samarjit Chakraborty, Tulika Mitra, Abhik Roychoud...