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FCCM
2003
IEEE
135views VLSI» more  FCCM 2003»
15 years 5 months ago
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
Benjamin A. Levine, Herman Schmit
ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
15 years 5 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
ARCS
2005
Springer
15 years 5 months ago
An FPGA Dynamically Reconfigurable Framework for Modular Robotics
Dynamic Reconfiguration has always constituted a challenge for embedded systems designers. Nowadays, technological developments make possible to do it on Xilinx FPGAs, but setting...
Andres Upegui, Rico Moeckel, Elmar Dittrich, Auke ...
ASPDAC
2007
ACM
135views Hardware» more  ASPDAC 2007»
15 years 3 months ago
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
- Most image processing applications are computationally intensive and data intensive. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these a...
Yazhuo Dong, Yong Dou
FCCM
2000
IEEE
133views VLSI» more  FCCM 2000»
15 years 4 months ago
Configuration Caching Management Techniques for Reconfigurable Computing
Although run-time reconfigurable systems have been shown to achieve very high performance, the speedups over traditional microprocessor systems are limited by the cost of configur...
Zhiyuan Li, Katherine Compton, Scott Hauck