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DATE
2007
IEEE
81views Hardware» more  DATE 2007»
15 years 6 months ago
Improving utilization of reconfigurable resources using two dimensional compaction
Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the rec...
Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. ...
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
15 years 3 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
FCCM
2004
IEEE
144views VLSI» more  FCCM 2004»
15 years 3 months ago
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
Matthias Dyer, Marco Platzner, Lothar Thiele
FPL
2007
Springer
80views Hardware» more  FPL 2007»
15 years 6 months ago
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi,...
LCPC
2005
Springer
15 years 5 months ago
A Language for the Compact Representation of Multiple Program Versions
Abstract. As processor complexity increases compilers tend to deliver suboptimal performance. Library generators such as ATLAS, FFTW and SPIRAL overcome this issue by empirically s...
Sébastien Donadio, James C. Brodman, Thomas...