3104 search results - page 363 / 621 » A High Performance Kernel-Less Operating System Architecture |
130
Voted
WSC
1997
15 years 4 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
136
Voted
DAC
2008
ACM
16 years 4 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
VLSID
2003
IEEE
16 years 3 months ago
2003
IEEE
This paper quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module i...
116
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VLSID
2005
IEEE
16 years 3 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
144
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HPDC
2007
IEEE
15 years 9 months ago
2007
IEEE
Grid computations require global access to massive data stores. To meet this need, the GridNFS project aims to provide scalable, high-performance, transparent, and secure wide-are...