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» A High Performance Kernel-Less Operating System Architecture
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ECRTS
2006
IEEE
15 years 9 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
NETWORK
2007
163views more  NETWORK 2007»
15 years 2 months ago
A Cross-Layering Design for IPv6 Fast Handover Support in an IEEE 802.16e Wireless MAN
Broadband wireless access networks, such as the IEEE 802.16 standard for wireless metropolitan area networks (WMANs), aim to provide high bandwidth, low-cost, scalable solutions t...
Youn-Hee Han, Heejin Jang, JinHyeock Choi, Byungjo...
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 3 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
DATE
2010
IEEE
144views Hardware» more  DATE 2010»
15 years 8 months ago
A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation
—Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low comput...
Abdulkadir Akin, G. Sayilar, Ilker Hamzaoglu
CF
2006
ACM
15 years 9 months ago
A nano-scale reconfigurable mesh with spin waves
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...
Mary Mehrnoosh Eshaghian-Wilner, Alexander Khitun,...