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» A Higher-Level Language for Hardware Synthesis
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DATE
2005
IEEE
164views Hardware» more  DATE 2005»
15 years 3 months ago
Automated Synthesis of Assertion Monitors using Visual Specifications
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
Ambar A. Gadkari, S. Ramesh
ESORICS
2006
Springer
15 years 1 months ago
Policy-Driven Memory Protection for Reconfigurable Hardware
Abstract. While processor based systems often enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reconfigurable har...
Ted Huffmire, Shreyas Prasad, Timothy Sherwood, Ry...
ACSD
2009
IEEE
106views Hardware» more  ACSD 2009»
14 years 7 months ago
Teak: A Token-Flow Implementation for the Balsa Language
This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise hands...
Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
15 years 3 months ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 1 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem