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» A Logic for Application Level QoS
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BMCBI
2004
185views more  BMCBI 2004»
14 years 10 months ago
Linear fuzzy gene network models obtained from microarray data by exhaustive search
Background: Recent technological advances in high-throughput data collection allow for experimental study of increasingly complex systems on the scale of the whole cellular genome...
Bahrad A. Sokhansanj, J. Patrick Fitch, Judy N. Qu...
ET
2002
122views more  ET 2002»
14 years 10 months ago
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function
LVDS is the acronym for Low-Voltage-DifferentialSignaling and is described in both the ANSI/TIA/EIA644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made ...
Magnus Eckersand, Fredrik Franzon, Ken Filliter
OOPSLA
2009
Springer
15 years 4 months ago
Enhancing source-level programming tools with an awareness of transparent program transformations
Programs written in managed languages are compiled to a platform-independent intermediate representation, such as Java bytecode. The relative high level of Java bytecode has engen...
Myoungkyu Song, Eli Tilevich
ESOP
2005
Springer
15 years 3 months ago
Asserting Bytecode Safety
Abstract. We instantiate an Isabelle/HOL framework for proof carrying code to Jinja bytecode, a downsized variant of Java bytecode featuring objects, inheritance, method calls and ...
Martin Wildmoser, Tobias Nipkow
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
14 years 1 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...