This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...
Parkinson, Bornat, and Calcagno recently introduced a logic for partial correctness in which program variables are treated as resource, generalizing earlier work based on separati...
of the Reliant Telco Platform, K. Wiesneth Safety-oriented INTERBUS INTERBUS Safety-, K. Meyer-Graefe Developing a Binding Process for Automated Program Recognition and Fault Local...
CLF (the Concurrent Logical Framework) is a language for specifying and reasoning about concurrent systems. Its most significant feature is the first-class representation of concu...
Kevin Watkins, Iliano Cervesato, Frank Pfenning, D...
Abstract. The paper presents a high performance True Random Number Generator (TRNG) embedded in Altera Stratix Field Programmable Logic Devices (FPLDs). As a source of randomness, ...