3239 search results - page 542 / 648 » A Logical Process Calculus |
FPGA
2001
ACM
15 years 5 months ago
2001
ACM
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
ICCS
2001
Springer
15 years 5 months ago
2001
Springer
Nowadays, people start to accept fuzzy rule–based systems as flexible and convenient tools to solve a myriad of ill–defined but otherwise (for humans) straightforward tasks s...
115
Voted
ADAEUROPE
2000
Springer
15 years 5 months ago
2000
Springer
of the Reliant Telco Platform, K. Wiesneth Safety-oriented INTERBUS INTERBUS Safety-, K. Meyer-Graefe Developing a Binding Process for Automated Program Recognition and Fault Local...
ITC
1998
IEEE
15 years 5 months ago
1998
IEEE
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
104
click to vote
ARVLSI
1997
IEEE
15 years 5 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...